Publications

• D. Calsi, V. Zaccaria, Interruptible Remote Attestation of Low-End IoT Microcontrollers via Performance Counters, ACM Transactions on Embedded Computing Systems (TECS), July 2023
• D. Carta, V. Zaccaria, G. Quagliarella, M. Molteni, Efficient Attack-Surface Exploration for Electromagnetic Fault Injection, Proceedings of COSADE 2023: Constructive Side-Channel Analysis and Secure Design, March 2023, pp 23 to 41
• V. Zaccaria, The propagation game: on simulatability, correlation matrices, and probing security, ArXiv (also in IACR ePrint), February 2023
• M. Molteni, V. Zaccaria, V. Ciriani, ADD-based Spectral Analysis of Probing Security, Proceedings of DATE 2022: International Conference on Design, Automation and Test in Europe, March 2022, pp 987 to 992
• M. Molteni, V. Zaccaria, A relation calculus for reasoning about t-probing security, Journal of Cryptographic Engineering, 2022, pp 1 to 14
• M. Molteni, P. Juergen, V. Zaccaria, On robust strong‐non‐interferent low‐latency multiplications, IET Information Security, 2021, pp 127 to 132
• V. Zaccaria, An F-algebra for analysing information leaks in the presence of glitches, IACR, June 2020
• M. Molteni, V. Zaccaria, On the spectral features of robust probing security, IACR Transactions on Cryptographic Hardware and Embedded Systems, August 2020, pp 24 to 48
• V. Zaccaria, M. Molteni, F. Melzani, G. Bertoni, Darth's Saber: A Key Exfiltration Attack for Symmetric Ciphers Using Laser Light, Proceedings of FDTC 2018: Workshop on Fault Diagnosis and Tolerance in Cryptography, September 2018, pp 23 to 26
• F. Daniel, M. Matera, V. Zaccaria, A. Dell'orto, Toward Truly Personal Chatbots: On the Development of Custom Conversational Assistants, Proceedings of the 1st International Workshop on Software Engineering for Cognitive Services, 2018, pp 31 to 36
• V. Zaccaria, F. Melzani, G. Bertoni, Spectral features of higher-order side-channel countermeasures, IEEE Transactions on Computers, April 2018, pp 596 to 603
• F. Daniel, M. Matera, E. Quintarelli, L. Tanca, V. Zaccaria, Context-Aware Access to Heterogeneous Resources Through On-the-Fly Mashups, Proceedings of CAISE 2018: Conference on Advanced Information Systems Engineering, June 2018, pp 119 to 134
• L. Delledonne, V. Zaccaria, R. Susella, G. Bertoni, F. Melzani, CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks, ACM Transactions on Design Automation of Electronic Systems (TODAES), November 2018, pp 69:1 to 69:17
• E. Bisi, F. Melzani, V. Zaccaria, Symbolic analysis of higher-order side channel countermeasures, IEEE Transactions on Computers, June 2017, pp 1099 to 1105
• V. Cassani, S. Gianelli, M. Matera, R. Medana, E. Quintarelli, L. Tanca, V. Zaccaria, On the Role of Context in the Design of Mobile Mashups, Proceedings of RMC 2016: Rapid Mashup Development Tools, Revised Selected Papers, June 2016, pp 108 to 128
• G. Mariani, G. Palermo, V. Zaccaria, C. Silvano, DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling, IEEE Transactions on Computer Aided Design of Integrated Circuits, 2015, pp 293 to 306
• E. Paone, F. Robino, G. Palermo, V. Zaccaria, I. Sander, C. Silvano, Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints, Proceedings of DATE 2015: International Conference on Design, Automation and Test in Europe, March 2015, pp 736 to 741
• S. Xydis, G. Palermo, V. Zaccaria, C. Silvano, SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis, IEEE Transactions on Computer Aided Design of Integrated Circuits, January 2015, pp 155 to 159
• G. Massari, E. Paone, P. Bellasi, G. Palermo, V. Zaccaria, W. Fornaciari, C. Silvano, Combining application adaptivity and system-wide Resource Management on multi-core platforms, Proceedings of SAMOS 2014: XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, July 2014, pp 26 to 33
• D. Gadioli, S. Libutti, G. Massari, E. Paone, M. Scandale, P. Bellasi, G. Palermo, V. Zaccaria, G. Agosta, W. Fornaciari, C. Silvano, OpenCL Application Auto-tuning and Run-Time Resource Management for Multi-core Platforms, Proceedings of ISPA 2014: IEEE International Symposium on Parallel and Distributed Processing with Applications, August 2014, pp 127 to 133
• E. Paone, D. Gadioli, G. Palermo, V. Zaccaria, C. Silvano, Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications, Proceedings of ASAP 2014: IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, June 2014, pp 161 to 168
• G. Massari, E. Paone, M. Scandale, P. Bellasi, G. Palermo, V. Zaccaria, G. Agosta, W. Fornaciari, C. Silvano, Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures, Proceedings of ARC 2014: Reconfigurable Computing: Architectures, Tools, and Applications - 10th International Symposium, April 2014, pp 345 to 352
• G. Mariani, G. Palermo, V. Zaccaria, C. Silvano, DeSpErate: Speeding-up Design Space Exploration by using Predictive Simulation Scheduling, Proceedings of DATE 2014: International Conference on Design, Automation and Test in Europe, March 2014, pp 1 to 4
• G. Mariani, V. Sima, G. Palermo, V. Zaccaria, G. Marchiri, C. Silvano, K. Bertels, Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction, Proceedings of FPL 2013: International Conference on Field Programmable Logic and Applications, September 2013, pp 1 to 8
• V. Zaccaria, Keynote: Principles of Design Space Exploration in the Embedded Multi-core Era, undefined, 2013, pp 1
• A. Ashouri, V. Zaccaria, S. Xydis, G. Palermo, C. Silvano, A Framework for Compiler Level Statistical Analysis over Customized VLIW Architecture, Proceedings of VLSI-SoC 2013: International Conference on Very Large Scale Integration and System-on-Chip, October 2013, pp 124 to 129
• G. Mariani, G. Palermo, V. Zaccaria, C. Silvano, ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models, Parallel Computing, September 2013, pp 504 to 519
• E. Paone, N. Vahabi, V. Zaccaria, C. Silvano, D. Melpignano, G. Haugou, T. Lepley, Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models, Proceedings of DATE 2013: International Conference on Design, Automation and Test in Europe, March 2013, pp 671 to 676
• S. Xydis, G. Palermo, V. Zaccaria, C. Silvano, A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization, Proceedings of DATE 2013: International Conference on Design, Automation and Test in Europe, March 2013, pp 659 to 664
• G. Mariani, G. Palermo, V. Zaccaria, C. Silvano, Design Space Exploration and Run-time Resource Management for Multi-cores, ACM Transactions on Embedded Computing Systems (TECS), September 2013, pp 20:1 to 20:27
• V. Zaccaria, Keynote: Design space exploration and run-time resource management in the embedded multi-core era, undefined, 2012, pp 1
• C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J. Zins, H. Hubert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-couvreur, I. Anagnostopoulos, A. Bartzas, D. Soudris, T. Kempf, G. Ascheid, J. Ansari, P. Mahonen, B. Vanthournout, Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach, Proceedings of INA-OCMC 2012: Interconnection Network Architecture: On-Chip, Multi-Chip, January 2012, pp 39 to 42
• E. Paone, G. Palermo, V. Zaccaria, C. Silvano, D. Melpignano, G. Haugou, T. Lepley, An Exploration Methodology for a Customizable OpenCL Stereo-Matching Application Targeted to an Industrial Multi-Cluster Architecture, Proceedings of CODES+ISSS 2012: International Conference on Hardware/Software codesign and System Synthesis, October 2012, pp 503 to 512
• G. Mariani, G. Palermo, V. Zaccaria, C. Silvano, Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework, Proceedings of the ARCS Workshops 2012, February 2012, pp 363 to 374
• S. Marceglia, S. Bonacina, V. Zaccaria, C. Pagliari, F. Pinciroli, How might the iPad change healthcare?, Journal of the Royal Society of Medicine, June 2012, pp 233 to 241
• G. Palermo, C. Silvano, V. Zaccaria, A Variability-Aware Robust Design Space Exploration Methodology for on-Chip Multiprocessors Subject to Application Specific Constraints, ACM Transactions in Embedded Computing Systems, July 2012, pp 29:1 to 29:28
• G. Mariani, V. Sima, G. Palermo, V. Zaccaria, C. Silvano, K. Bertels, Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures, Proceedings of DATE 2012: IEEE Design, Automation and Test Conference in Europe, March 2012, pp 1379 to 1384
• G. Mariani, G. Palermo, C. Silvano, V. Zaccaria, OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces, IEEE Transactions on Computer Aided Design of Integrated Circuits, May 2012, pp 740 to 753
• C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J. Zins, H. Hubert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-couvreur, I. Anagnostopoulos, A. Bartzas, D. Soudris, T. Kempf, G. Ascheid, J. Ansari, P. Mahonen, B. Vanthournout, Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach, Proceedings of ReCoSoC 2011: Reconfigurable Communication-centric Systems-on-Chip, June 2011, pp 1 to 7
• D. Matos, G. Palermo, V. Zaccaria, C. Reinbrecht, A. Susin, C. Silvano, L. Carro, Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip, Proceedings of NoCArc 2011: 4th International Workshop on Network on Chip Architectures, December 2011, pp 31 to 36
• C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J. Zins, D. Siorpaes, H. Huebert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-couvreur, A. Bartzas, D. Soudris, T. Kempf, G. Ascheid, H. Meyr, J. Ansari, P. Mahonen, B. Vanthournout, Parallel Paradigms and Run-time Management Techniques for Many-core Architectures: 2PARMA Approach, Proceedings of INDIN 2011: IEEE Conference on Industrial Informatics, July 2011, pp 835 to 840
• C. Silvano, W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martinez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, C. Ykman-couvreur, M. Wouters, C. Kavka, L. Onesti, A. Turco, U. Bondi, G. Mariani, H. Posadas, E. Villar, C. Wu, F. Dongrui, Z. Hao, T. Shibin, MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures, Lecture Notes in Electrical Engineering, Vol. 57 - Selected Papers from VLSI 2010 Annual Symposium, N. Voros et al. (Eds.), 2011, pp 47 to 63
• C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Melpignano, J. Zins, D. Siorpaes, H. Huebert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, R. Meyr, J. Ansari, P. Mahonen, B. Vanthournout, 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures, Lecture Notes in Electrical Engineering, Vol. 57 - Selected Papers from VLSI 2010 Annual Symposium, N. Voros et al. (Eds.), 2011, pp 65 to 79
• G. Mariani, C. Ykman-couvreur, P. Avasare, G. Vanmeerbeeck, G. Palermo, C. Silvano, V. Zaccaria, Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming, Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, Cristina Silvano, William Fornaciari, Eugenio Villar (Eds.), 2011, pp 189 to 204
• C. Kavka, L. Onesti, E. Rigoni, A. Turco, S. Bocchio, F. Castro, G. Palermo, C. Silvano, V. Zaccaria, G. Mariani, F. Dongrui, Z. Hao, T. Shibin, Design Space Exploration of Parallel Architectures, Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, Cristina Silvano, William Fornaciari, Eugenio Villar (Eds.), 2011, pp 171 to 187
• P. Avasare, C. Ykman-couvreur, G. Vanmeerbeeck, G. Mariani, G. Palermo, C. Silvano, V. Zaccaria, Design Space Exploration Supporting Run-Time Resource Management, Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, Cristina Silvano, William Fornaciari, Eugenio Villar (Eds.), 2011, pp 93 to 107
• G. Palermo, C. Silvano, V. Zaccaria, E. Rigoni, C. Kavka, A. Turco, G. Mariani, Response Surface Modeling for Design Space Exploration of Embedded Systems, Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, Cristina Silvano, William Fornaciari, Eugenio Villar (Eds.), 2011, pp 75 to 91
• E. Rigoni, C. Kavka, A. Turco, G. Palermo, C. Silvano, V. Zaccaria, G. Mariani, Optimization Algorithms for Design Space Exploration of Embedded Systems, Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, Cristina Silvano, William Fornaciari, Eugenio Villar (Eds.), 2011, pp 51 to 73
• C. Silvano, W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martinez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, C. Ykman-couvreur, M. Wouters, C. Kavka, L. Onesti, A. Turco, U. Bondi, G. Mariani, H. Posadas, E. Villar, C. Wu, F. Dongrui, Z. Hao, The MULTICUBE Design Flow, Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, Cristina Silvano, William Fornaciari, Eugenio Villar (Eds.), 2011, pp 3 to 17
• G. Mariani, G. Palermo, V. Zaccaria, C. Silvano, ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems, Proceedings of SASP 2011: IEEE Symposium on Application Specific Processors, June 2011, pp 86 to 93
• C. Ykman-couvreur, P. Avasare, G. Mariani, G. Palermo, C. Silvano, V. Zaccaria, Linking run-time resource management of embedded multi-core platforms with automated design-time exploration, Computers Digital Techniques, IET, March 2011, pp 123 to 135
• C. Silvano, W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martinez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, C. Ykman-couvreur, M. Wouters, C. Kavka, L. Onesti, A. Turco, U. Bondi, G. Mariani, H. Posadas, E. Villar, C. Wu, F. Dongrui, Z. Hao, T. Shibin, MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures, Proceedings of ISVLSI 2010: IEEE Annual Symposium on VLSI, July 2010, pp 488 to 493
• C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Siorpaes, H. Huebert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, R. Meyr, J. Ansari, P. Mahonen, B. Vanthournout, 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures, Proceedings of ISVLSI 2010: IEEE Annual Symposium on VLSI, July 2010, pp 494 to 499
• G. Mariani, A. Brankovic, J. Jovic, G. Palermo, V. Zaccaria, C. Silvano, A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip, Proceedings of DAC 2010: Design Automation Conference, June 2010, pp 120 to 125
• V. Zaccaria, G. Palermo, F. Castro, C. Silvano, G. Mariani, Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors, Proceedings of 2PARMA: Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, February 2010, pp 325 to 331
• A. Gellert, A. Florea, L. Vintan, G. Palermo, V. Zaccaria, C. Silvano, Energy-Performance Design Space Exploration of SMT Architectures Exploiting Selective Load Value Predictions, Proceedings of DATE 2010: IEEE Design, Automation and Test Conference in Europe, March 2010, pp 271 to 274
• G. Mariani, P. Avasare, G. Vanmeerbeeck, C. Ykman-couvreur, G. Palermo, C. Silvano, V. Zaccaria, An industrial design space exploration framework for supporting run-time resource management on multi-core systems, Proceedings of DATE 2010: IEEE Design, Automation and Test Conference in Europe, March 2010, pp 196 to 201
• A. Choudury, G. Palermo, C. Silvano, V. Zaccaria, Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips, Proceedings of NoCArc '09: International Workshop on Network on Chip Architectures, December 2009, pp 37 to 42
• G. Palermo, C. Silvano, V. Zaccaria, ReSPIR: A Response Surface-based Pareto Iterative Refinement for Application-Specific Design Space Exploration, IEEE Transactions on Computer Aided Design of Integrated Circuits, December 2009, pp 1816 to 1829
• G. Mariani, G. Palermo, C. Silvano, V. Zaccaria, A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip, Proceedings of IEEE Symposium on Application Specific Processors 2009, July 2009, pp 21 to 28
• G. Mariani, G. Palermo, C. Silvano, V. Zaccaria, Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip, Proceedings of Euromicro Conference on Digital System Design (DSD), August 2009, pp 383 to 389
• G. Mariani, G. Palermo, C. Silvano, V. Zaccaria, Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques, Proceedings of IEEE IC-SAMOS'09 - International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation, July 2009, pp 118 to 124
• G. Palermo, C. Silvano, V. Zaccaria, A DoE/RSM-based Strategy for an Efficient Design Space Exploration targeted to CMPs, Proceedings of RAPIDO 2009: Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, January 2009
• G. Palermo, C. Silvano, V. Zaccaria, Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures, Proceedings of IEEE/ACM ASPDAC 2009: Asia and South Pacific Design Automation Conference, January 2009, pp 323 to 328
• V. Zaccaria, Data Flow Deadlock Avoidance for Streaming Applications Mapped on Network-on-Chips, Workshop on Streaming Systems: From Web and Enterprise to Multicore (in conjunction with IEEE/ACM Micro-41), November 2008
• G. Palermo, C. Silvano, V. Zaccaria, Robust Optimization of SoC Architectures: A Multi-Scenario Approach, Proceedings of ESTIMEDIA 2008: IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, October 2008, pp 7 to 12
• G. Mariani, G. Palermo, C. Silvano, V. Zaccaria, An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks, Proceedings of IFIP VLSI-SOC 2008: International Conference on Very Large Scale Integration, October 2008, pp 213 to 218
• G. Palermo, C. Silvano, V. Zaccaria, Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration, Proceedings of DSD 2008: IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools, September 2008, pp 641 to 644
• G. Palermo, C. Silvano, V. Zaccaria, An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods, Proceedings of IC-SAMOS 2008: International Conference on Embedded Computer Systems Architectures, Modeling and Simulation, July 2008, pp 150 to 157
• G. Palermo, C. Silvano, V. Zaccaria, An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints, Proceedings of SASP 2008: IEEE Symposium on Application Specific Processors, June 2008, pp 75 to 82
• A. Pagni, F. Lucini, D. Pau, A. Borneo, V. Zaccaria, Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product, US 7243213, July 2007
• A. Bona, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, Reducing the Complexity of Instruction-Level Power Models for VLIW Processors, Design Automation for Embedded Systems, July 2006, pp 49 to 67
• G. Bertoni, L. Breveglieri, M. Monchiero, G. Palermo, V. Zaccaria, A Power Attack Methodology to AES Based on Induced Cache Misses: Procedure, Evaluation and Possible Countermeasures, New Trends in Cryptographic Systems, N. Nedjah and L.M. Mourelle (Eds.), 2006, pp 37 to 52
• M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, D. Pau, R. Zafalon, Processor architecture, US 6889317, May 2005
• G. Bertoni, V. Zaccaria, L. Breveglieri, M. Monchiero, G. Palermo, AES Power Attack Based on Induced Cache Miss and Countermeasure, Proceedings of ITCC 2005: International conference on Information Technology, April 2005, pp 586 to 591
• G. Palermo, C. Silvano, V. Zaccaria, Multi-Objective Design Space Exploration of Embedded Systems, Journal of Embedded Computing, 2005, pp 305 to 316
• C. Silvano, M. Monchiero, G. Palermo, M. Sami, V. Zaccaria, R. Zafalon, Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach, Integration, The VLSI Journal, January 2005, pp 515 to 524
• A. Bona, V. Zaccaria, R. Zafalon, System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip, Proceedings of DATE 2004: IEEE Design, Automation and Test Conference in Europe, February 2004, pp 318 to 323
• M. Monchiero, G. Palermo, M. Sami, C. Silvano, V. Zaccaria, R. Zafalon, Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors, Proceedings of GLSVLSI 2004: Great Lakes Symposium on VLSI, April 2004, pp 440 to 443
• A. Bona, V. Zaccaria, R. Zafalon, System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip, Ultra Low-Power Electronics and Design, E. Macii (ed.), 2004, pp 233 to 254
• A. Bona, V. Zaccaria, R. Zafalon, Low Effort, High Accuracy Network-on-Chip Power Macro Modeling, Proceedings of PATMOS 2004: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, September 2004, pp 541 to 552
• G. Palermo, C. Silvano, V. Zaccaria, Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture, Proceedings of DATE 2003 Designers Forum: IEEE Design, Automation and Test Conference in Europe, March 2003, pp 20182
• G. Palermo, C. Silvano, V. Zaccaria, A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems, Proceedings of PATMOS 2003: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, September 2003, pp 249 to 258
• G. Bertoni, A. Bircan, L. Breveglieri, P. Fragneto, M. Macchetti, V. Zaccaria, About the performance of the advanced encryption standard in embedded systems with cache memory, Proceedings of ISCAS 2003: IEEE Int. Symposium on Circuits and Systems, May 2003, pp 145 to 148
• G. Palermo, C. Silvano, S. Valsecchi, V. Zaccaria, A System-Level Methodology for Fast Multi-Objective Design Space Exploration, Proceedings of GLSVLSI 2003: Great Lakes Symposium on VLSI, April 2003, pp 92 to 95
• G. Palermo, C. Silvano, V. Zaccaria, R. Zafalon, Branch Prediction Techniques for Low-Power VLIW Processors, Proceedings of GLSVLSI 2003: Great Lakes Symposium on VLSI, April 2003, pp 225 to 228
• V. Zaccaria, M. Sami, D. Sciuto, C. Silvano, Power Estimation and Optimization Methodologies for VLIW-based Embedded Systems, , April 2003, pp 203
• L. Salvemini, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems, Proceedings of SAC 2003: Symposium on Applied Computing, March 2003, pp 672 to 678
• M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, An Instruction-Level Energy Model for Embedded VLIW Architectures, IEEE Transactions on Computer Aided Design of Integrated Circuits, September 2002, pp 998 to 1010
• A. Bona, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, Energy estimation and optimization of embedded VLIW processors based on instruction clustering, Proceedings of DAC 2002: Design Automation Conference, June 2002, pp 886 to 891
• L. Benini, D. Bruni, M. Chinosi, C. Silvano, V. Zaccaria, R. Zafalon, A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems, Design Automation for Embedded Systems, October 2002, pp 183 to 203
• W. Fornaciari, D. Sciuto, C. Silvano, V. Zaccaria, A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems, Design Automation for Embedded Systems, September 2002, pp 7 to 33
• M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, Low-Power Data Forwarding for VLIW Embedded Architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, October 2002, pp 614 to 622
• A. Bona, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, An instruction-level methodology for power estimation and optimization of embedded VLIW cores, Proceedings of DATE 2002: IEEE Design, Automation and Test Conference in Europe, March 2002, pp 1128 to 1128
• V. Zaccaria, Power exploration methodologies for VLIW-based systems, , 2002
• V. Zaccaria, Power Exploration Methodologies for VLIW-based Systems, New Orleans, LA - USA, June 2002
• L. Benini, D. Bruni, M. Chinosi, C. Silvano, V. Zaccaria, R. Zafalon, A Power Modeling and Estimation Framework for VLIW-based Embedded Systems, Proceedings of PATMOS 2001: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, September 2001
• W. Fornaciari, D. Sciuto, C. Silvano, V. Zaccaria, A Design Framework to Efficiently Explore Energy-Delay Tradeoffs, Proceedings of CODES 2001: 9th ACM/IEEE International Symposium on Hardware/Software Co-Design, April 2001, pp 260 to 265
• A. Bona, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores, Dipartimento di Elettronica e Informazione - Politecnico di Milano, November 2001
• W. Fornaciari, V. Piuri, A. Prestileo, V. Zaccaria, An Agent-based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems, Proceedings of MATA 2001: Third International Workshop On Mobile Agents For Telecommunication Applications, August 2001, pp 153 to 162
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